OSD Quantifiable Assurance (QA) Workshop, Washington DC, Title: Quantifiable Assurance under Zero Trust
ERI Summit – Hardware Security Workshop, Detroit, MI, Title: Securing Supply Chain from Chips to PCBs
GomacTech 2019, New Mexico, March 2019, Title: The Pursuit of Happiness: Establishing hardware root of Trust for cybersecurity (Keynote Address)
NXP Semiconductors, Chandler, AZ, October 2018, Title: New Trends and Challenges in Securing Hardware
ISTFA 2018, Phoenix, AZ, October 2018, Title: Hardware Root-of-Trust for Cyber Security: Uncovering the Role of Test and Failure Analysis in Enabling Cyber Defense (Keynote Address)
IEEE Asian Test Symposium (ATS), Hefei, China, October 2018, Title: Securing SoCs: Current Practices and Challenges (Keynote Address)
Georgia Tech, September 2018
IEEE World Conference on Information Security Applications, Jeju, Korea, August 2018 (Keynote Address)
Georgia Tech, IoT Summer School, August 2018
Distinguished Speaker Series, Navy Crane, IN, August 2018
SRC Workshop on Fabrics of the Security, Fremont, CA, July 2018 (Keynote Address)
NSF SCCS Workshop, Washington DC, March 2017, Title: SoC Security Validation
Cisco CRC workshop on Hardware Security, San Jose, CA, Dec. 2017
Groundswell Conference on Cybersecurity, Melbourne, FL, Title: When it Comes to Security, Do not Forget about Hardware (Keynote Speaker)
Qualcomm, San Diego, Beijing, October 2017, Title: SoC Security
Tsinghua University, Beijing, October 2017, Title: When it Comes to Security, Do not Forget about Hardware
Int. IEEE Verification and Security Workshop (IVSW), July 2017, Title: SoC Security: Current Practices and Recent Challenges (Keynote Address)
Air Force Research Laboratory (AFRL), Dayton, OH, June 2017, Title: Trusted and Assured Microelectronics
Air Force Research Laboratory (AFRL), Dayton, OH, June 2017, Title: Design-for-Anti-Counterfeit
Ohio State University, Columbus, OH, June 2017, Title: When It Comes to Cybersecurity, Do Not Forget About Hardware
IEEE Ambassador talk at the Harris Corporation, Melbourne, FL, March 2017, Title: When It Comes to Cybersecurity, Do Not Forget About Hardware
RSA Conference, Joint Talk with Cisco CTO for Global Value Chain Edna Conway, San Francisco, CA, February 2017, Title: Securing Electronic Supply Chain from Design to Resign
IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), Dec. 2016, Taiwan, Title: Security Rule Check (Keynote Address)
IEEE Microprocessor Test and Verification (MTV) Conference, Austin, TX, Dec. 2016, Title: Security Rule Check: A Closer Look at the Automated Test for Security (Keynote Address)
Global Foundries, CTO Speaker Series, Malta, NY, December 2016
Chinese Academy of Science (CAS), China, 2016
International Workshop on Hardware Security, China, 2016, Title: Hardware Security: Past, Present, and the Future (Keynote address)
Peking University, China, 2016
Beihang University, China, 2016
Dagstuhl Seminar, Germany, 2016, Title: Unlocking the potential of Hardware Security
IEEE International Reliability Physics Symposium (IRPS), 2016, Title: Security vs. Reliability: Where Do These Two Road Converge?
IEEE Workshop on CPS Security, April 2016, San Francisco, CA (Keynote Speaker)
US-Brazil Joint Workshop on Cybersecurity, April 2016, Orlando, FL (Keynote Speaker)
Florida Institute of Technology (FIT), Host: Dr. Fareena Saqib, Melbourne, FL, March 2016
Florida Energy Systems Consortium (FESC), March 2016
International Symposium on Quality Electronic Design (ISQED), Santa Clara, March 2016, Title: New Frontiers in Hardware Security and Trust (Keynote Address)
Northrop Grumman, Sep. 2015, Washington DC
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2015, Austin, TX
Potomac Institute for Policy (PIP), Oct. 2015
DHS Software and Supply Chain Assurance Forum, Nov. 2015
AMD, Boston, MA, Nov. 2007, Host: Dr. Kamran Zarrineh
Analog Devices, Boston, MA, Nov. 2007, Host: Harry Chen
Guest Speaker, Magma‘s Luncheon Event at International Test Conference (ITC), San Jose, CA, Tuesday, Oct. 23, 2007
Cadence, June 2007, Title: IR-drop Tolerant AT-speed Tests for Nanometer Technology Designs, Host: Dr. Krishna Chakravadhanula
LSI Logic, June 2007, Title: Generating High Quality At-speed Tests for Nanometer Technology Designs: Challenges and Solutions, Invited by: Dr. Sreejit Chakravarty
Qualcomm (San Diego, CA), June 2007, Title: At-speed Test for Nanotechnology: Challenges and Solutions, Host: Dr. Sagar Sabade
Guest Lecturer for VLSI System Testing Course of ECE Department at Duke University, Instructor: Prof. Krish Chakrabarty
Mentor Graphics (Wilsonville, OR), Nov. 2006, Title: At-speed Test for Nanotechnology: Challenges and Solutions, Host: Dr. Nilanjan Mukherjee
LSI Logic (San Jose, CA), Nov. 2006, Title: High Quality At-speed Tests for Nanotechnology Designs, Host: Dr. Arun Gunda
AMD (Sunnyvale, CA), Oct. 2006, Title: High Quality At-speed Tests for Nanometer High-speed Designs, Host: Dr. Anuja Sehgal
Texas Instruments (Dallas, TX), April 2004, Title: Enhanced Scan Architectures for Reducing Power and Test Application Time
Panels:
Panel Organizer/Moderator, IEEE HOST, CHIPS Act impact on Supply Chain, Onshoring, Assurance, and US Industry, May 2023
Panel Organizer/Moderator, GomacTech, Quantifiable Assurance: From IPs to SoCs, March 2022
Panelist: IEEE Workshop on Silicon Lifecycle Management (SLM), 2021
Panel Co-Organizer, High Level Synthesis: Facts, Myths, and Fantasies, IEEE HOST, Dec. 2020
Panelist: Quantifiable Assurance, IEEE HOST 2020
Panelist: Hardware Security, SRC SIA DOE workshop on Decadal Plan for Semiconductors, workshop on ICT Hardware Enabled Security
Panelist: Education and Workforce Development, ERI Summit, August 2020
Panelist, Assured AI, Trusted and Assured Microelectronic (TAME) Forum, Washington DC, May 2019
Panel Organizer/Moderator, Chip to PCB Assurance: Detection and Prevention, International Test Conference (ITC), 2019.
Panel Moderator, Chip to PCB Assurance: Detection and Prevention, IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), 2019.
Panel Organizer, Physical Inspection and Attacks: New Frontiers in Hardware Security, International Test Conference (ITC), 2018.
Panel Organizer, Crossroad Between Physical Inspection and Hardware Security, IEEE International Workshop on Physical Attacks and Inspection on Electronics (PAINE), San Francisco, June 2018.
Tutorial Organizer, DAC, Security of Internet of Things (IoT) and Cyber-Physical Systems (CPS): A Hands-on Approach, Presenter: Yier Jin, June 2018
Panelist, Hardware Supply Chain Security in Asia and Around the World, IEEE AsianHOST, 2018
Panelist, Trusted and Assured Microelectronics (TAME), Vision for TAME (co-located with HOST), May 2018
Panel Moderator, Fire Side Chat with Edna Conway, CSO of Cisco, Women in Hardware and Systems Security Workshop (WISE), May 2018
Panel Organizer, Global Electronic Supply Chain: What Can South East Asian do about it? IEEE AsianHOST, 2017
Panelist, NYU Alfred P. Sloan Foundation, 2017, Cybersecurity Lecture, with Wally Rhines, Chairman and CEO of Mentor Graphics, April 2017
Panelist, Internet of Things (IoT) and Automotive Security Workshop (IASW), 2017, Security for IoTs
Panel Organizer, International Test Conference, 2016, Test and Security for IoTs
Panelist, International Workshop on Hardware Security, 2016, Research Collaboration Opportunities in Hardware Security Areas
Panel Organizer, IEEE International Verification and Security Workshop (IVSW), 2016, Title: DFT vs. Security – Is it a Contradiction? How Can We Get the Best of Both Worlds?
Panel Organizer, IEEE International Hardware-Oriented Security and Trust (HOST), 2016, Title: Hardware-based System Security
Panel Organizer and Moderator, IEEE International Hardware-Oriented Security and Trust (HOST), 2016, Title: IP Protection from Chip-to-System Using Reverse Engineering
Panelist, International Symposium on Quality Electronic Design (ISQED), 2016, Title: Hardware and Systems Security Challenges in IoT Era
Panel Organizer / Panelist, IEEE VLSI Test Symposium (VTS), April 2016, Title: Test Opportunities for Secure Hardware
Panelist, Florida International University (FIU) Cybersecurity Meeting, Miami, FL, Oct. 2015
Panelist, IEEE Security and Privacy Symposium (S&P), San Jose, CA, May 2014
Panelist, SRC STARSS (), San Jose, CA, May 2014
Panelist, Microprocessor Test and Verification (MTV), Nov. 2013
Panelist, IEEE North Atlantic Test Workshop (NATW), May 2013
Panelist, Cisco Innovation Test Conference (CITC), 2012
Panel Moderator, Title: Low Power Testing, IEEE VLSI Test Symposium (VTS), May 2011
Panelist, International Test Conference (ITC), 2010
Panelist, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2010
Panelist, IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 2009
Panelist, International Test Conference (ITC), Nov. 2009, Austin, TX
Panel Organizer, Title: Test and Diagnosis for Parametric Failures, Int. Workshop on Defect and Data Driven Testing (D3T), Nov. 2009
Panel Organizer, Title: Zero Defect (Zero DPPM): How can we get there?, Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2008
Panel Co-organizer, Title: Challenges in Test Data Collection and Analysis, Int. Workshop on Defect and Data Driven Testing (D3T), Oct. 2008
Panelist, WRTLT, Sapporo, Japan, Nov. 2008.
Panel Co-organizer (with Hank Walker, Texas A&M University), Title: Process Variations + Systematic Defects: Can DBT Help? , International Workshop on Defect-Based Testing (DBT), 2007.
Panel Co-organizer (with Kee Sup Kim from Intel), Title: Three Questions to Oracle (Data required for test engineers and researchers in academia), IEEE VLSI Test Symposium (VTS), 2006
Proposal reviewer and panelist for the National Science Foundation (NSF), 2005, 2006, 2009
Tutorials:
IEEE International Hardware-Oriented Security and Trust (HOST), Secure Heterogeneous Integration, May 2023
International Test Conference (ITC), CAD for SoC Security Verification, September. 2022
IEEE International Hardware-Oriented Security and Trust (HOST), CAD Solutions for SoC Security, June 2022
Design, Automation, and Test in Europe (DATE), CAD for SoC Security, Feb. 2022
International Test Conference (ITC), SoC Security Verification, Oct. 2021
IEEE International Hardware-Oriented Security and Trust (HOST), CAD Solutions for SoC Security, Dec. 12, 2021
Design, Automation, and Test in Europe (DATE), CAD for SoC Security, Feb. 2021
IEEE International Hardware-Oriented Security and Trust (HOST), CAD for SoC Security, Dec. 2020
IEEE International Hardware-Oriented Security and Trust (HOST), 2019, CAD for Security
IEEE International Hardware-Oriented Security and Trust (HOST), 2018, Protecting Electronics Supply Chain from Design to Resign
IEEE International Hardware-Oriented Security and Trust (HOST), 2017, Protecting Electronics Supply Chain from Design to Resign
International Test Conference (ITC), 2016, Test Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits
International Test Conference (ITC), 2015, Test Opportunities and Challenges for Secure Hardware and Verifying Trust in Integrated Circuits, M. Tehranipoor (University of Florida) and D. Forte (University of Florida)
Design Automation Conference (DAC), 2015, Introduction to Hardware Security, M. Tehranipoor (University of Florida), M. Potkonjak (UCLA), and Ron Perez (CRI)
IEEE International System-on-Chip Conference (SOCC), 2014, Electronic Component Supply Chain Security: Threats, Challenges, and Solution, M. Tehranipoor (UCONN)
Design, Automation, and Test in Europe (DATE), 2014, All You Need to Know About Hardware Trojans and Counterfeit ICs, M. Tehranipoor and D. Forte (UCONN)
IEEE Conference on VLSI, 2014, All You Need to Know About Hardware Trojans and Counterfeit ICs, M. Tehranipoor and D. Forte (UCONN)
IEEE International Reliability Physics Symposium (IRPS), 2013, Chip to System Reliability Fundamentals, Mohammad Tehranipoor (UConn), Nemat Bidokhti (Cisco), and Bill Eklow (Cisco)
International Test Conference (ITC), 2011, Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices, Srivaths Ravi (Texas Instruments), Mohammad Tehranipoor (UConn), and Rohit Kapur (Synopsys)
International Test Conference (ITC), 2011, High-Quality and Low-Cost Delay Testing for VDSM Designs: Challenges & Solutions, Mohammad Tehranipoor (UConn), Krish Chakrabarty (Duke University), and Jeff Rearick (AMD)
Design Automation Conference (DAC), 2011, Chip to System Reliability Fundamentals, Mohammad Tehranipoor (UConn), Nemat Bidokhti (Cisco), and Bill Eklow (Cisco)
International Test Conference (ITC), 2010, Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices, Srivaths Ravi (Texas Instruments), Mohammad Tehranipoor (UConn), and Rohit Kapur (Synopsys)
International Test Conference (ITC), 2010, High-Quality and Low-Cost Delay Testing for VDSM Designs: Challenges & Solutions, Mohammad Tehranipoor (UConn), Krish Chakrabarty (Duke University), and Jeff Rearick (AMD)
Design, Automation, and Test in Europe (DATE), 2010, Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices, Srivaths Ravi (Texas Instruments), Mohammad Tehranipoor (UConn), Rohit Kapur (Synopsys)
International Conference on VLSI, 2009, High-Quality and Low-Cost Delay Testing for VDSM Designs: Challenges & Solutions, Mohammad Tehranipoor (UConn) and Krish Chakrabarty (Duke University)
Midwest Symposium on Circuits and Systems (MWSCAS), 2008, Title: High-Quality Delay Tests for Nanometer Technology Designs
Selected Presentations:
SRC Annual Grant Review, 2011, Arizona State University
Design, Automation, and Test in Europe (DATE), 2010, Title: High-Quality Pattern Selection for Screening Small-Delay Defects Considering Process Variations and Crosstalk
Design, Automation, and Test in Europe (DATE), 2010, Title: Novel Physical Unclonable Function Based on Process and Environmental Variations
IEEE Int. Workshop on Hardware-Oriented Security and Trust (HOST), 2009
Int. Conference on Computer-Aided Design (ICCAD), 2008
Int. Symposium on Defect and Fault Tolerance (DFT), Oct. 2008
Title: Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
Int. Workshop on Hardware-Oriented and Security (HOST), June 2008
Title: Detection of Malicious Inclusions in Secure Hardware: Challenges and Solutions
Design, Automation & Test in Europe (DATE), March 2008
Title: Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
SRC Annual Review, 2010
SRC Annual Review, 2009
SRC Annual Review, 2008
SRC Annual Grant Review, 2007, Duke University, NC, Title: At-speed Transition Delay Test Using Low-Cost Testers
IEEE North Atlantic Test Workshop (NATW), 2007, Boxborough, MA, Title: IR-drop Tolerant Transition Delay Fault Testing in SOC Designs
ICCAD, Oct. 2006, Title: A Novel Framework for Faster-than-at-Speed Test Considering IR-drop Effects
DBT 2006, Title: Improving ATPG and Pattern Generation Selection for Screening Small Delay Defects
SRC Annual Grant Review, 2006, UCSB, CA, Title: At-speed Transition Delay Test Using Low-Cost Testers
Design Automation Conference (DAC), 2006
Title: A Hybrid FPGA Using Nanoscale Cluster and CMOS Scale Routing
Title: Timing-Based Delay Test for Screening Small Delay Defects
IEEE VLSI Test Symposium (VTS), Elevator Talk, 2006, Title: IR-Drop Effects on Faster-than-at-speed Delay Test
IEEE North Atlantic Test Workshop (NATW), 2005, Title: At-Speed Transition Fault Testing Using Low Speed Testers with Application to Reduced Scan Enable Routing Area
IEEE VLSI Test Symposium (VTS), 2005: Title: At-Speed Transition Fault Testing With Low Speed Scan Enable
Midwest Symposium on Circuits and Systems (MWSCAS), 2005
Title: Architecture of an Embedded Queue Management Engine for High-Speed Network Devices
